Partitioning and mapping communication graphs on a modular reconfigurable parallel architecture

Abstract

A reconfigurable parallel architecture whose interconnection topology can be dynamically modified in order to match the communication characteristics of a given algorithm provides flexibility for efficient execution of various applications. But, due to communication links switching devices design constraints, connecting a large number of processors on a dynamically programmable interconnection structure, leads to the design of a modular interconnection structure. The validation of such a modular reconfigurable interconnection network is based on the demonstration of its ability to support any application coded as communicating sequential processes. This demonstration leads to the mapping problem of any partitionable communicating processes graph on the defined architecture, taking into account communication constraints of the modular and reconfigurable interconnection network. This paper presents results obtained in the context of a research project named MODULOR which objectives were the design and the realization of a massively parallel reconfigurable computer, as well as of the software tools needed for developing applications that efficiently use reconfiguration potentialities of the architecture.