A hierarchy preserving hierarchical compactor

Abstract

A one-dimensional IC layout compactor is presented which simultaneously compacts the contents of all cells of the layout hierarchy without changing this hierarchy. The compactor performs both compaction and wire length minimization hierarchically using the power of the Simplex method for linear programs. Compaction of arrays of overlapping cells and symmetry preserving compaction are also handled, since these are special cases of layout hierarchies. Using dedicated simplex algorithms for compaction and wire length minimization, a globally optimal result is produced quickly and efficiently, without the use of protection frames or domains and terminals. The compactor corrects design rule violations, preserves wire widths, and maintains terminal connections automatically. It does not yet introduce jogs in wires automatically. Results are provided for a few CMOS modules, including a ROM and a SRAM core.