Solving satisfiability problems on FPGAs using experimental unit propagation heuristic

Abstract

This paper presents new results on an approach for solving satisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Arrays (FPGAs). This approach has become feasible due to recent advances in Reconfigurable Computing. We develop an algorithm that is suitable for a logic circuit implementation. This algorithm is basically equivalent to the Davis-Putnam procedure with Experimental Unit Propagation. The required hardware resources for the algorithm are less than those of MOM’s heuristics.