Abstract
Settling time is one of the most important performance parameters for a whole class of amplifier, such as those employed in switched-capacitor-based circuits and analog-to-digital converters. In this work, analysis to predict and to minimize the settling time for amplifiers characterized by first-, second-, and third-order system-wise behaviour, is developed. The proposed method is very useful for design purposes. It allows amplifier poles to be placed directly in the complex plane, achieving the best-settled time response in accord with the desired accuracy level. © Springer-Verlag Berlin Heidelberg 2007.
Cite
CITATION STYLE
Pugliese, A., Cappuccino, G., & Cocorullo, G. (2007). Settling time minimization of operational amplifiers. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4644 LNCS, pp. 107–116). Springer Verlag. https://doi.org/10.1007/978-3-540-74442-9_11
Register to see more suggestions
Mendeley helps you to discover research relevant for your work.
