An Implementation of Nine-Level Hybrid Cascade Multi-level Inverter (HCMLI) Using IPD-Topology for Harmonic Reduction

Abstract

Nowadays, multi-level inverters (MLI) with different topologies are used for various industrial applications. For average and large power applications, three commonly used topologies of MLI are flying capacitor, diode clamped and cascaded. This chapter implements the nine-level asymmetric cascaded multi-level inverter with IM for various kinds of modulation techniques in MATLAB/ Simulink. Increase in number of inverter levels, the response has more number of staircase steps available to achieve the required wave shape. As more number of steps is added to the output, waveform will lead to decrease in harmonics with the increase in levels, also the voltage across the devices connected in cascade increases.