Performance analysis of array multiplier using low-power 10T full adder

Abstract

Multipliers are used in arithmetic and logic unit (ALU) and the performance of multiplier greatly depends on the number of adder cells. A study and performance investigation of array multiplier using low-power 10T full adder is presented. One of the crucial circuits in all digital devices is the adder cell and it is used in ALU. In this work, various performance parameters including power consumption, delay, and power-delay product are compared with full adder, array multiplier using 10T full-adder and static energy-recovery full (SERF) adder-based techniques. Array multipliers realized that using 10T-based full-adder circuit consumes less power when compared to SERF techniques. Simulation results show that the power consumption of array multiplier using 10T full-adder and SERF technique is 673.7 µW and 1.042 mW, respectively, which is less than the power consumption of conventional array multiplier. The power consumption and delay of proposed Array Multiplier are obtained using 180nm CMOS process.