Design, test and evaluation of trace-buffer inserted FPGA system

Abstract

Integrated circuits have more functionality and complexity, and to verify that these devices working properly in all scenarios is a difficult task. For using traditional verification techniques such as software simulation, designers are taking advantage of the significantly higher clock speeds which can be achieved by using field-programmable gate-array (FPGA)-based prototypes. However, the major challenge of using FPGAs for verification and debug is observability. Designers must use special techniques to observe the values of FPGA’s internal signals. In this paper, a new method has been proposed for increasing the observability of FPGAs and demonstrates its feasibility. The new method incrementally inserts the Trace-Buffers controlled by a trigger into already placed-and-routed FPGA designs.