FPGA implementation of RECTANGLE block cipher architectures

Abstract

In recent time, various lightweight algorithms have been proposed to provide security in a constrained resource environment. With so many algorithms and their different implementations, it is hard to choose the appropriate security primitive for an application. In this work, various hardware implementations of lightweight block cipher RECTANGLE is proposed like Iterative design, 16-bits architecture, Reduced Substitution box design, RAM-based design and Iterative design with Partial loop unrolled. These designs provide aid in overcoming the problem of security in a constrained resource environment. Architectures are designed and implemented in various FPGA platforms. Results are extensively evaluated and compared on the basis of throughput, throughput/slice, area utilization, energy requirement and power consumption for their implementation in different FPGA platforms. Best trade-off among throughput and area is given by Iterative design with partial loop unrolling. It also gave best energy consumption values for all FPGAs. Ram-based design utilized least number of registers for its implementation.