This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit's noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit's parameters and selected performance metrics is also highlighted. © 2009 Springer Berlin Heidelberg.
CITATION STYLE
Figueiredo, M., & Aguiar, R. L. (2009). A study on CMOS time uncertainty with technology scaling. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5349 LNCS, pp. 146–155). https://doi.org/10.1007/978-3-540-95948-9_15
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