Rapid and reliable routability estimation for FPGAs

Abstract

Modern large scale FPGA designs require interconnect estimation for cutting down the design cycle times. Most of the available estimation techniques use empirical methods to estimate routability. These methods lack the ability to accurately model back-end routers and the estimation results produced are not very reliable. We recently proposed a fast and generic routability estimation method, fGREP [1], that predicts the peak routing demand and the channel occupancies in a given FPGA architecture. The peak demands are within 3 to 4% of actual detailed routing results produced by the well known physical design suite, VPR [2]. In this paper, we observe that, fGREP spends a significant portion of its execution time in estimating the demands for nets with large number of terminals. We propose a new routability estimation method based on fGREP which offers significant speedups over fGREP, while maintaining the same high levels of accuracy. The new method is up to 36× faster than fGREP, and on an average is about 102× faster than VPR's detailed router. © Springer-Verlag Berlin Heidelberg 2002.