Abstract
In the paper the authors present an implementation of the algorithm of DV Decoder conformant to IEC-61834-2 standard in re-programmable resources. A software implementation has been realized and then transferred to the Handel-C language. By parallelization of the algorithm and using language mechanisms in Handel-C the processing efficiency has been increased 10 times with respect to the initial hardware implementation. The implementation has been verified in hardware-software environment with real data transmitted on-line from a DV cam-corder. © Springer-Verlag Berlin Heidelberg 2006.
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CITATION STYLE
Cichoń, S., Gorgoń, M., & Pac, M. (2006). Handel-C design enhancement for FPGA-based DV decoder. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3985 LNCS, pp. 128–133). Springer Verlag. https://doi.org/10.1007/11802839_18
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