A high power MOS-FET with a vertical drain electrode and meshed gate structure

Abstract

A p-channel power MOS-FET is developed which exhibits 20A current, 3Ω transconductance and 85 V breakdown voltage in a 5 × 5 mm2 chip. The features of the device structure are a vertical drain electrode which enables to use most of the surface area for the source electrode and a meshed gate structure which makes it possible for the channel width per unit area to become twice as large as that of a conventional MOS-FET, thereby drain current of the device can be increased. The device with an offset gate structure was fabricated from an n on p+ epitaxial wafer by using the poly silicon gate and the ion implantation processes. The device does not show local current concentration, thermal runaway or second breakdown. Stable operation is obtained at ambient temperatures up to 180°C, which is attributed to a negative temperature coefficient of the drain current. © 1976 The Japan Society of Applied Physics.