Built-in reliability investigation of gate-drain underlapped pnin-gaa-tfet for improved linearity and reduced intermodulation distortion

Abstract

This work investigates the built-in reliability of four different TFET candidates by assessing the linearity performance and harmonic distortion (HD). The Gate-Drain Underlapped, n+pocket, cylindrical GAA-TFET (GDU-PNIN-GAA-TFET), a result of the amalgamation of two highly successful engineering schemes and a potential transistor candidate as a result of analog performance improvements in other respects, forms the primary device whose linearity/HD parameters are analyzed through industry-standard linear performance metric like VIP2, VIP3, IIP3, ZCP and P1dB, HD2 and HD3, respectively. In order to gauge the progressive improvement of the GDU-PNIN-GAA-TFET, the simulation results for the intermediate engineered devices (GDU-GAA-TFET, PNIN-GAA-TFET) are compared with those of the conventional TFET. A remarkable improvement in the performance of GDU-PNIN-GAA-TFET is observed. This indicates the possibility of operation of the GDU-PNIN-GAA-TFET as a reliable device for future low-power, high-frequency wireless applications that are peeping over the horizon.