A novel low power multiply–accumulate (MAC) unit design for fixed point signed numbers

Abstract

In the emerging technologies the low power designs play a critical role of operations. Our proposed work is on the low power MAC unit that is used to find the fixed point signed numbers. The proposed design is to achieve high throughput and low power consumption. Our proposed work has various building blocks like firstly, Wallace tree multiplier since a multiplier is one of the key part for the processing of digital signal processing systems and secondly an accumulation block. Since the output from the multiplier and adder is to be efficient, we proposed a BCD block that is used to convert the output into BCD number. The overall MAC is performed in the cadence virtuoso 90 nm technology and performance analysis of each individual block is examined using the cadence virtuoso before designing the overall MAC unit. Power, delay and power-delay product are calculated using the Cadence Spectre tool.