Software verification technology has the potential to improve the quality of software. The basic technique is to generate verification conditions for a given program and to discharge these proof obligations using a theorem prover. Encoding the verification conditions is a delicate process, not just because it must capture the intended programming semantics, but also because it must yield formulas that a theorem prover can process effectively. In this talk, I will discuss the process of generating verification conditions in the program verifier for the object-oriented language Spec#. I will highlight design decisions we have made in modeling programs and targeting SMT solvers, lessons we have learned, and challenges that remain ahead. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Leino, K. R. M. (2007). Designing verification conditions for software. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4603 LNAI, p. 345). Springer Verlag. https://doi.org/10.1007/978-3-540-73595-3_23
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