Speeding up attribute reduction process is an important issue in data mining. The goal of this paper is to compare two hardware implementations of minimal reducts computation, i.e. the previously introduced implementation on Intel Arria V SoC and a newly proposed solution on Xilinx Zynq Ultrascale+ MPSoC. Two versions of an attribute reduction algorithm, i.e. blind and frequency based breadth search strategies, were implemented on the two frameworks. Experimental research showed that finding minimal reducts can be accelerated several times when using the new device.
CITATION STYLE
Choromański, M., Grześ, T., & Hońko, P. (2019). Two FPGA devices in the problem of finding minimal reducts. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 11703 LNCS, pp. 410–420). Springer Verlag. https://doi.org/10.1007/978-3-030-28957-7_34
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