Research and implementation of reconfigurable multiplier over galois field targeted at stream cipher

Abstract

Multiplication over Galois field is the core operation in stream cipher. Based on the conversion of polynomial basis over different finite fields, a reconfigurable hardware architecture for multiplier over Galois field is presented. The multiplier can perform multiplications over GF((2 8)4) , GF((28)2), GF(232) , GF(216), GF(28) with one single hardware architecture. The design has been realized using Altera's FPGA of the family of Stratix II, the result indicates that the hardware spending is saved with one single multiplier. And when the multiplication over GF(232) is performed, the clock frequency is up to 70.22Mhz, the data throughput can achieve 4.83Gbps, and the area only takes 586 ALUTS. © 2009 Springer Berlin Heidelberg.