In this paper, we propose a new next generation high-performance micro-architecture based on the combination of simultaneous multithreading and trace processor. By exploiting both Instruction-Level Parallelism and Thread-Level Parallelism, Simultaneous Multithreading Trace Processor can be expected to achieve higher performance than SMT or Trace Processor individual. We describe the organization of SMT Trace Processor architecture and some fundamental techniques. A path-based multiple traces prediction mechanism is also described in the paper. © Springer-Verlag Berlin Heidelberg 2003.
CITATION STYLE
Wang, K. F., Ji, Z., & Hu, M. (2003). Simultaneous multithreading trace processors. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2834, 96–103. https://doi.org/10.1007/978-3-540-39425-9_10
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