Abstract
In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.
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CITATION STYLE
APA
Wang, X., Bryant, A., Dokumaci, O., Oldiges, P., & Haensch, W. (2007). Simulation study of multiple FIN FinFET design for 32nm technology node and beyond. In 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 (pp. 125–128). Springer-Verlag Wien. https://doi.org/10.1007/978-3-211-72861-1_30
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