Design of GaAs Flip-Flop Using Depletion-Mode-Only Transistors

Abstract

In this paper, the design of logic gates based on GaAs 0.5 µm pHEMT technology is proposed. It uses Depletion-mode-only transistors, which is applicable to technological processes without Enhancement-mode transistors available. An attempt has been made to reduce power consumption by using high-value resistors. Basic logic gates (inverter, NOR, NAND) have been implemented and the topology of flip-flop has been designed, alongside with the NAND gate. The results of this design can be used for any desirable logic circuit, combinational or sequential.