Graceful degradation in performance of WaveScalar architecture

Abstract

With the advancement in technology in the field of transistors it has become easy to have millions of transistors on one dice. It is still a challenge to translate the available resources into convenient application. Many conventional processors has failed to achieve that level of performance. A new alternative to the conventional processors is the scalable WaveScalar. WaveScalar is a dataflow instruction set based execution model with low complexity and high performance features. It can run real world programs, non-real world programs without changing the language and still having the same parallelism. It is designed as a intelligent memory system where each instruction executes in its place and then communicates with its dependent. If a high-performance processor is to realize its full potential, complexity should be least. Here is this paper, we have proposed solution to reduce the complexity of the wavescalar processor without affecting its performance. © Springer-Verlag Berlin Heidelberg 2010.