FPGA implementation of a rational adder

Abstract

A systolic coprocessor for the addition of signed normalized rational numbers is implemented using field programmable logic from Atmel. The circuit is structured as a sandwich of systolic arrays implementing the necessary subtasks: integer GCD, exact division, multiplication and addition/subtraction. In particular, the implementation of GCD and of exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are performed least-significant digits first, which allows bit-pipelining between partial operations at reduced area-cost. The actual implementation for 8-bit operands consumes 730 cells (3,500 equivalent gates) and runs at 25 MHz (5 MHz after layout).