Selection of Voltage Thresholds for Delay Measurement

Abstract

Since all physical devices have a finite non-zero response time, the notion of delay between the input and output logic signals arises naturally once digital abstraction is done. This delay should be positive and non-zero, since a physical device takes a finite amount of time to respond to the input. Defining a strictly positive delay is not a problem in the abstract domain of logic signals, since input and output "events" are precisely defined. However, when the signal non-idealities are accounted for, the notion of events is blurred and it is not obvious how to define delay such that it reflects the causal relationship between the input and the output. By necessity, we define the start and end points of these events by determining the time instants when the signals cross some appropriate voltage thresholds. The selection of these voltage thresholds for logic gates as well as simple interconnect wires, is the subject of this paper. We begin by a discussion of what we mean by signal delay and how it arises in a logic gate. With this background, starting from ideal inputs to ideal inverters and concluding with physical inputs to physical inverters, we examine the problem of threshold selection for inverters through a logical sequence of model refinement, using a combination of analytical and experimental techniques. Based on the insight gained through this analysis, we examine the problem for multi-input (both static and dynamic) gates as well as point-to-point interconnect wires. We show that thresholds derived from the gate's DC voltage transfer characteristic removes the anomalies, such as negative delay and large sensitivity to input waveshape effects, that can arise with the widely used 50% and 10%-90% thresholds. Despite its fundamental nature, however, we note that the problem of threshold selection has received scant attention in the literature. To the best of our knowledge, this is the first detailed study of this problem.