FPGA-Based High-Performance Computing Platform for Cryptanalysis of AES Algorithm

Abstract

Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AES key search engines, an efficient key generator is also proposed in this work. The proposed architecture achieves a computational complexity of 2124 for an attack against 10-rounds AES algorithm.