Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic

Abstract

Dynamically reconfigurable FPGAs are increasingly being used to speed up algorithms that would previously have been executed on computers. Reconfiguration latency is the time that elapses between a request for new circuitry to be loaded onto an FPGA and the point at which the circuitry is ready for use. It is a critical parameter in the design of dynamically reconfigurable systems used for algorithm acceleration and needs to be evaluated early in the design cycle. This paper reports on the development of expert system techniques for the a priori estimation of reconfiguration latency.