A brief summary of VSPEC

Abstract

This paper provides an overview of the VSPEC behavioral interface specification language for VHDL. Although operational specification language such as VHDL provide exceptional specification capabilities, at the systems requirements level the operational style is a hindrance. VSPEC provides VHDL users with a declarative mechanism for defining functional requirements and performance constraints. In the tradition of behavioral interface specification languages, VSPEC adds clauses to the VHDL entity construct allowing axiomatic specification of functional requirements. Because system constraints play an ever increasing role in systems design, VSPEC also provides performance constraint specification capability. This paper presents the basics of VSPEC, its semantics, semantic analysis, and briefly describes current and future applications.