Exploring FaultoTolerant Network-on-Chip Architectures [37]

Abstract

The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analyses of these reliability hazards and the incorporation of comprehensive protection measures into all NoC designs. In this chapter, the author examines the impact of these transient and permanent failures on the reliability of on-chip interconnects and develops comprehensive counter-measures to either prevent or recover from them. In this regard, several novel schemes are proposed to remedy various kinds of soft and hard error symptoms, while keeping area and power overhead at a minimum. The proposed solutions are architected to fully exploit the available infrastructures in an NoC and enable versatile reuse of valuable resources. The effectiveness of the proposed techniques has been validated using a cycle-accurate simulator.