Efficient FPGA-based Karatsuba multipliers for polynomials over F 2

Abstract

We study different possibilities of implementing the Karatsuba multiplier for polynomials over F2 on FPGAs. This is a core task for implementing finite fields of characteristic 2. Algorithmic and platform dependent optimizations yield efficient hardware designs. The resulting structure is hybrid in two different aspects. On the one hand, a combination of the classical and the Karatsuba methods decreases the number of bit operations. On the other hand, a mixture of sequential and combinational circuit design techniques includes pipelining and can be adapted flexibly to time-area constraints. The approach - both theory and implementation - can be viewed as a further step towards taming the machinery of fast algorithmics for hardware applications. © Springer-Verlag Berlin Heidelberg 2006.