Analysis of MTCMOS Cache Memory Architecture for Processor

Abstract

In this paper, power reduction technique is applied over SRAM and sense amplifier and then calculate the power consumption through cadence tool. Over the conclusion of analysis, A Architecture of cache memory has been done with lowest leakage power. In this paper from different sense amplifiers, we conclude that Charge-Transfer SA have lowest power dissipation, i.e.,11.06 µW. SRAM has 220.078 µW power dissipation after applying leakage power reduction technique such as MTCMOS_technique, Footer Stack Technique, Sleepy Keeper Technique and Sleep-Stack Technique, and there is 98–99% reduction and 75–76% reduction in Charge-Transfer SA. So, after all conclusion, architecture has been made with MTCMOS SRAM memory and MTCMOS Charge-Transfer SA with 98% reduction in power dissipation. This paper describes that MTCMOS_technique applied over different circuits reduces leakage power reduction as well as SRAM and CTSA with MTCMOS_technique in architecture gives low power consumption for a cache memory.