Design and implementation of a high-speed reconfigurable modular arithmetic unit

Abstract

A high-performance and dynamic reconfigurable modular arithmetic unit is presented, which provides full support to modulo 28/2 16/232 addition and modulo232/ 2 16+1/232-1 multiplication operation. To save the hardware cost, we have adopted sharing technique to implement modular multiplication operation, and then optimized each critical block. The design has been realized using Altera's FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18μm SMIC process. The result proves that the propagation time of the critical path is 6.04ns. Compared with other designs, the reconfigurable modular arithmetic unit not only supports for diverse modular arithmetic in the block ciphers, but also provides IP Core for reconfigurable cryptographic system. © Springer-Verlag Berlin Heidelberg 2007.