Accuracy enhancement by selective use of branch history in embedded processor

Abstract

The branch prediction accuracy is one of essential parts of performance improvement in embedded processors as well as modern microarchitectures. Until now, the length of branch history has been statically fixed for all branch instructions, and the history length is usually selected in accordance with the size of prediction table. In this paper, we propose a dynamic per-branch history length adjustment policy, which can dynamically change the history length for each branch instruction. The proposed solution tracks data dependencies of branch instructions and identifies strongly correlated branches in branch history. Compared to the previous bimodal style predictors and the fixed history length predictors in embedded processors, our method provides better history length for each branch instruction, resulting in substantial improvement in prediction accuracy. © Springer-Verlag Berlin Heidelberg 2006.