Abstract
A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipelined systolic array architecture suitable to perform real-time soft morphological filtering is presented as an illustrative example. The processing times of the proposed hardware structure do not depend on the data window size and its hardware complexity grows linearly with the number of its inputs.
Cite
CITATION STYLE
Gasteratos, A., Andreadis, I., & Tsalides, P. (1997). A new hardware structure for implementation of soft morphological filters. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1296, pp. 488–494). Springer Verlag. https://doi.org/10.1007/3-540-63460-6_154
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