This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family. © 2010 Springer-Verlag.
CITATION STYLE
Penneman, N., Perneel, L., Timmerman, M., & De Sutter, B. (2010). An FPGA-based real-time event sampler. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5992 LNCS, pp. 364–371). https://doi.org/10.1007/978-3-642-12133-3_35
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