Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms

Abstract

We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presented in this work is the highest in terms of throughput for any of SHA-3 candidates, achieving a figure of 13.67Gbps for Keccak-256 on Virtex 6. This can enable line rate operation for hashing on 10Gbps network interfaces. © 2012 Springer-Verlag.