High speed JPEG coder based on modularized and pipelined architecture with distributed control

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Abstract

The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.25μm CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported. © Springer-Verlag Berlin Heidelberg 2005.

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APA

Mujahid, F. A., Jung, E. G., Har, D. S., Hong, J. H., & Lim, H. J. (2005). High speed JPEG coder based on modularized and pipelined architecture with distributed control. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3767 LNCS, pp. 466–476). https://doi.org/10.1007/11581772_41

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