Design of low power SAR ADC with two different DAC structure and two different SAR logic designs and their comparisons

Abstract

Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper the power consumption and linearity of SAR ADC are analyzed by using different DAC structures and different SAR Logics. Three types of DAC structures i.e. Capacitive DAC, R-2R resistive DAC, and a CMOS R-2R ladder DAC is employed. Coming to SAR logic, sequential/code register and non-redundant SAR logics are used. Among the all, the CMOS R-2R ladder DAC and non-redundant SAR logic structured SA-ADC is efficient and provides optimum results for all circuit design aspects i.e. power, speed, and area. Along above all designs a dynamic two-stage comparator and the D flip-flops with transmission gates are used due to their energy efficiency and capability of working in low supply voltages.