The paper considers in detail the feasibility of constructing a digital analogue computer (or differential analyser) on the basis of full-word or total transfer, rather than the incremental transfer which has been preferred in the past. After an analysis of the errors inherent in the integrating routine, and the possibilities for electronic patching, values are proposed for word length and sampling period. The paper concludes by suggesting a possible architecture for such a computer and discusses briefly the advantages it has to offer and the problems that must be faced in marketing it. © 1980, All rights reserved.
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