Bus and memory interference in double bus multiprocessor systems

Abstract

Exact and approximate markovian models are developed for the performance analysis of four multiprocessor architectures based on the availability of two global busses for the interconnection of processors and shared resources such as common memories, I/O devices, etc. The performance index used in the paper is the average number of active processors, called processing power. Exact models show a combinatorial growth of the number of states of the Markov process, whereas the number of states of the approximate models grows linearly with the number of processors in the system. The accuracy of the results yielded by the approximate models is discussed, comparing the processing power estimates with exact results and with simulation. The uniform view used in the development of the models allows a comparison of the efficiency of the four architectures for a given load. © 1984.