Floating-point analog-to-digital converters (FP-ADCs) were developed and used to quantize wide dynamic range signals in applications where large signals need not be encoded with a precision greater than that required for small ones. Comparing floating point with uniform quantization, it was shown that FP-ADC provides smaller relative quantization error and higher dynamic range for the same resolution, but at the cost of doubling the conversion time. To improve the accuracy and speed of conversion of such an FP-ADC, a higher precision predictive floating-point architecture was conceived (PFP-ADC). The PFP-ADC consists of two parallel uniform A/D converters, a D/A converter, a fixed-gain amplifier and a subtraction circuit. The current subtrahend of the subtraction circuit is a prediction based on the previous acquisitions, while the current minuend is the measured signal itself. Determination of mantissa and exponent occurs in parallel. This paper presents both the principle used to improve the resolution of the FP-ADCs and the FPGA implementation of the PFP-ADC proof-of-concept. © 2003 Elsevier Ltd. All rights reserved.
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