Mechanical stress is a major concern in microelectronics: reliability of VLSI interconnects is mainly controlled by the stress levels. The increasing complexity of processes and the shrinking of feature sizes make necessary to use quantitative modelling in order to optimise process parameters and device geometries. We had developed a method based on the use of some finite element analysis (FEA) tools, to quantitatively determine the stress evolution along the process flow. This method allows us to simulate material deposition, etching and thermal ramping steps. It was used to monitor the stress level is in two metallic levels interconnected by a via during the fabrication. Our numerical results were analysed regarding the so-called stress-voiding phenomenon: these results allow us to point out the critical interface to focus on. All the obtained results are in good agreement with experimental observations. This method can be used to determine the evolution of the most probable void position as the geometry varies and then to optimise both the geometry and the process to minimize stress-induced voiding. © 2006 Elsevier Ltd. All rights reserved.
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