This article describes a new generalized integrator with an improved performance. It has a partially digital architecture. For high speed operation, digital information is processed at incremental intervals rather than at sample by sample instants. This feature is implemented without precluding neither the direct interfacing of the unit to the analogue computer nor the provision of an economical computing unit. The proposed structure has been simulated, constructed and applied to solve some problems with accurate results. © 1986.
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