Some 2D arrays composed of nanometer-size islands exhibit very large fluctuations in the current responses. The model and numerical tool presented here show that such devices are characterized by a dominant conduction path. In this paper, we explain the origin of this important noise, and suggest a design modification to reduce it. Then the same model is applied to a floating gate array (FG) on top of a tiny channel (FG-MOS). We show that in order to avoid giant current variations in the read process, large tunnel junctions are prerequisite between FG and channel, yet also between dots within the FG, even if the latter process is not correlated to the FG total retention time. © 2003 Elsevier Ltd. All rights reserved.
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