A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

  • Yabuuchi M
  • Nii K
  • Tsukamoto Y
 et al. 
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Abstract

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

Author-supplied keywords

  • 45nm
  • 8T
  • DVFS
  • SRAM
  • assist circuit
  • cross point

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Authors

  • M. Yabuuchi

  • K. Nii

  • Y. Tsukamoto

  • S. Ohbayashi

  • Y. Nakase

  • H. Shinohara

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