An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-□, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-μm CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz. ©2009 IEEE.
CITATION STYLE
Chung, Y. M., & Wei, C. L. (2009). An all-digital phase-locked loop for digital power management integrated chips. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2413–2416). https://doi.org/10.1109/ISCAS.2009.5118287
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