Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (rlc) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance. © 2000 IEEE.
CITATION STYLE
Davis, J. A., & Meindl, J. D. (2000). Compact distributed rlc interconnect models-part I: Single line transient, time delay, and overshoot expressions. IEEE Transactions on Electron Devices, 47(11), 2068–2077. https://doi.org/10.1109/16.877168
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