This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary-weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm2 in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.
CITATION STYLE
Syed, A., Ahmed, E., Maksimović, D., & Alarcón, E. (2004). Digital pulse width modulator architectures. In PESC Record - IEEE Annual Power Electronics Specialists Conference (Vol. 6, pp. 4689–4695). https://doi.org/10.1109/PESC.2004.1354828
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