Dynamic cluster assignment mechanisms

  • Canal R
  • Parcerisa J
  • Gonzalez A
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Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster microarchitecture with a naive code partitioning approach: integer instructions are allocated to one cluster and floating-point instructions to the other. This partitioning scheme is simple and results in no communications between the two clusters (just through memory) but it is in general far from optimal because she workload is not evenly distributed most of the time. In fact, when the processor is running integer programs, the workload is extremely unbalanced since the FP cluster is not used at all. In this work we investigate run-time mechanisms that dynamically distribute the instructions of a program among these two clusters. By optimizing the trade-off between inter-cluster communication penalty and workload balance, the proposed schemes can achieve an average speed-up of 36% for the SpecInt95 benchmark suite

Author-supplied keywords

  • Computer aided instruction
  • Decoding
  • FP cluster
  • Hardware
  • Instruction sets
  • Irrigation
  • Logic
  • Microarchitecture
  • Proposals
  • Read-write memory
  • Registers
  • cluster assignment mechanisms
  • inter-cluster communication
  • microarchitectures
  • naive code partitioning
  • parallel architectures
  • resource allocation
  • run-time mechanisms
  • workload balance

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  • R. Canal

  • J.M. Parcerisa

  • A. Gonzalez

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