FPGA implementation of discrete fractional fourier transform

Abstract

Since decades, fractional Fourier transform has taken a considerable attention for various applications in signal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the real time computation of discrete fractional Fourier transform is essential in those applications. On this context, we have proposed new hardware architecture for implementing a Discrete Fractional Fourier Transform (DFrFT) which requires hardware complexity of O(4N), where N is transform order. This proposed architecture has been simulated and synthesized using verilogHDL, targeting a FPGA device (XLV5LX110T). The simulation results are very close to the results obtained by using MATLAB. The result shows that, this architecture can be operated on a maximum frequency of 217MHz. © 2010 IEEE.