H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency relative to former standards at the expense of higher computational requirements. Implementing the H.264 video encoder for an embedded System-on-Chip (SoC) is a big challenge. For an efficient implementation, we motivate the use of multiprocessor platforms for the execution of a parallel model of the encoder. In this paper, we propose a high-level independent target-architecture parallelization methodology for the development of an optimized parallel model of a H.264/AVC encoder (i.e. a processes network model balanced in communication and computation workload). © 2009 EDAA.
CITATION STYLE
Zrida, H. K., Jemai, A., Ammari, A. C., & Abid, M. (2009). High level H.264/AVC video encoder parallelization for multiprocessor implementation. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 940–945). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/date.2009.5090800
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