Higher order autocorrelation vision chip

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Abstract

This paper describes very large scale integration implementation using a new vision chip architecture specialized for target tracking and recognition. A 64 × 64 pixel prototype vision chip and its evaluation results are shown. The extraction algorithms of both higher order local autocorrelation (HLAC) features and moment features are implemented on the prototype chip in order to achieve high-speed image processing and enhanced pixel integration. The chip is integrated on a 5.00 mm × 5.00 mm chip using a 0.35-μm CMOS DLP/TLM process; the pixel size 44.2 μm × 48.3 μm. The maximum current consumption is approximately 400 mA, and the chip can calculate all HLAC features more than 26 times in 1 ms. The experimental results also demonstrate that the chip can successfully recognize and count high-speed objects at real time. © 2006 IEEE.

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Ishii, I., Yamamoto, K., & Kubozono, M. (2006). Higher order autocorrelation vision chip. IEEE Transactions on Electron Devices, 53(8), 1797–1804. https://doi.org/10.1109/TED.2006.878024

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